1. Field of the Invention
The present invention relates to a method of operating a semiconductor memory, and more particularly, to a method of operating a P-channel memory.
2. Description of the Related Art
Among the various types of non-volatile memory products, electrical erasable and programmable read only memory (EEPROM) device is a memory device that has been widely used inside personal computer systems and electron equipment. In the EEPROM, data can be stored, read out or erased many numerous times and stored data are retained even after power is cut off.
A typical EEPROM includes a doped polysilicon floating gate and a doped polysilicon control gate. In the prior art technology, a charge trapping layer replaces the polysilicon floating gate. The material of the charge trapping layer can be, for example, silicon nitride. In general, an oxide layer is formed both above and below the silicon nitride charge-trapping layer to form a stacked structure including an oxide-nitride-oxide (ONO) composite layer. Read-only memory having this type of stacked gate structure is often referred to as a silicon-oxide-nitride-oxide-silicon (SONOS) memory device.
Generally, the memory devices are classified into P-channel memory and N-channel memory based on the type of channel. Wherein, a channel hot electron injection (CHEI) mode or a Fowler-Hordheim (FN) tunneling effect is used to program or erase the N-channel memory. The operation according to the FN tunneling effect requires high operational voltages, high power consumption and more process time. To enhance electron tunneling efficiency and device integrity, the thickness of the tunnel oxide of the memory is reduced. Due to shrinkage of the device, the interface breakdown voltage of the tunnel oxide declines as well. It cannot stand the high voltage applied for the FN tunneling effect. As a result, issues of increase of leakage current and deterioration of the memory reliability occur.
On the other hand, the P-channel memory has high device integrity, eliminates the reliability issue resulting from the hot hole injection, and generates low electrical field in the oxide layer during the electron injection. The electron injection speed of the P-channel memory is faster than that of the N-channel memory. The P-channel memory also consumes less power and energy, and requires low programming voltages. It thus has been widely used in semiconductor-related fields.
FIG. 1 is a drawing showing a prior art method of operating a P-channel memory. The method is similar to that described in U.S. Pat. No. 6,801,456. The P-channel memory includes the substrate 100, the ONO layer 110 (which is composed of the silicon oxide layer 102, the silicon nitride layer 104 and the silicon oxide layer 106) on the substrate 100, the P-type doped polysilicon gate 120 on the ONO layer 110, and the source 130a and the drain 130b, which are disposed in the substrate 100 adjacent to two sides of the ONO layer 110. During the erasing operation, 0V is applied to the source 130a and the drain 130b; −6V is applied to the gate 120; 6V is applied to the substrate 100. Accordingly, the FN tunneling effect or hot hole injection effect erases the data stored therein.
Since the FN tunneling effect or the hot hole injection effect is used for the P-channel memory, its operational efficiency is low. In order to enhance the operational efficiency, a high voltage should be applied to increase current. During the erasing operation, the voltage differential between the gate 120 and the substrate 100 is 12V. It results in high power consumption and requires more process time. Moreover, the high voltage causes high leakage currents and reduces the reliability of the memory device. In addition, by the device shrinkage, the leakage current issue becomes even more serious. That will restrain the extent to which device dimensions can shrink.